In order to increase the bandwidth efficiency and robustness against distortions, optical communication systems require modulation formats of higher order like, e.g., 100 Gbit/s coherently demodulated polarization multiplex of quaternary phase-shift keying (CP-QPSK). Hence, both polarizations (e.g., x-polarization and y-polarization) of PolMUX and the constellations of the complex signal (QPSK) are utilized for conveying data (e.g., as symbols).
With the modulation format increasing, the symbol rate in the optical system is reduced. For example, in the case of 100 Gbit/s CP-QPSK with 4 bits per symbol, the symbol rate amounts to 100/4=25 GSymbols/s. This makes the transmission more robust against optical distortions like chromatic dispersion (CD) or polarization mode dispersion (PMD). Such reduction of the symbol rate also allows for less processing power at the receiver.
A typical arrangement of a coherent receiver used in a conventional CP-QPSK optical communication system is shown in FIG. 1. An input 101 to the coherent receiver 100 is connected to a polarization beamsplitter 102. The polarization beamsplitter 102 has first output 103, transmitting the first polarization component PolX, and a second output 104 transmitting the second polarization component PolY. The first output 103 of the polarization beamsplitter 102 is connected to a first 90° optical hybrid 105, while the second output 104 of the polarization beamsplitter 102 is connected to a second 90° optical hybrid 106. A receiver local oscillator (LO) 107 has a first output 108 connected to the first 90° optical hybrid 105 and a second output 109 connected to the second 90° optical hybrid 106. A first output port 137 of the first 90° optical hybrid 105 is connected to a first photodetector 141, while a second output port 138 of the first 90° optical hybrid 105 is connected to a second photodetector 110. A first output port 119 of the second 90° optical hybrid 106 is connected to a third photodetector 120, while a second output port 121 of the second 90° optical hybrid 106 is connected to a fourth photodetector 122. The output 111 of the first photodetector 141 is fed to a first low pass filter 113, and the outputs 112, 139 and 140 respectively of the second 110, third 120 and fourth 122 photodetectors are fed respectively to a second 114, third 123, and fourth 124 low pass filters. The output of the first low pass filter 113, namely the in-phase signal IX 115 of the first polarization component PolX 103, is connected to a first analog-to-digital converter (ADC) 117. The output of the second low pass filter 114, namely the quadrature signal QX 116 of the first polarization component PolX 103, is connected to a second analog-to-digital converter (ADC) 118. The output of the third low pass filter 123, namely the in-phase signal IY 125 of the second polarization component PolY 104, is connected to a third analog-to-digital converter (ADC) 127. The output of the fourth low pass filter 124, namely the quadrature signal QY 126 of the second polarization component PolY 104, is connected to a fourth analog-to-digital converter (ADC) 128. The four free-running analog-to-digital converters (ADC) 117, 118, 127 and 128 are all fed by the clock 129 working at the frequency fADC. The outputs of the four analog-to-digital converters (ADC) 117, 118, 127 are connected to a digital signal processing (DSP) unit 130 where the fully digitized signal is then processed by a fully digital clock recovery unit 131 followed by an equalization unit 132, a carrier recovery unit 133, a first 134 and a second 135 comparator circuits and a decoding unit 136.
FIG. 2 shows a conventional clock recovery arrangement implemented as a second order Phase Locked Loop (PLL) 200 with an active PI-filter 201 (i.e. a filter with perfect integrator path) and a Gardner Phase Detector (PD) 202. The in-phase signal IX 205 is supplied to the first analog-to-digital converter (ADC) 206, which is fed by the clock 207 working at the frequency fADC, while the quadrature-phase signal QX 208 is supplied to the second analog-to-digital converter (ADC) 206, which is fed by the clock 207 working at the frequency fADC. The outputs 211 and 212 of the analog-to-digital converters (ADC) 206 and 210 are connected to an interpolation unit 204. The first output IXcorr(k) 213 and the second output QXcorr(k) 214 of the interpolation unit 204 are each supplied to a Gardner Phase Detector (PD) 202. The output 215 of the Gardner Phase Detector (PD) 202 is supplied to an active PI-filter 201 (i.e. filter with perfect integrator path) whose output 217 is connected to a Numerically Controlled Oscillator (NCO) 203. The output ε 216 of the Numerically Controlled Oscillator (NCO) 203 is fed to the interpolation unit 204. The outputs 211 and 212 of the analog-to-digital converters (ADC) 206 and 210 include about two samples per symbol. The exact value depends on the difference between the clock frequency fADC 207 and 209 of the ADCs 206 and 210 and twice the symbol frequency of the received signal (here called symbol frequency offset ΔfSym). For correction of ΔfSym and the initial phase shift of the ADCs 206 and 210, the sampled signal is interpolated in the interpolation unit 204 at the time instants ε produced by the numerically controlled oscillator NCO 203 of the digital PLL. The Gardner Phase Detector (PD) 202 uses three samples for calculation of the overall timing error. A conventional Gardner Phase Detector is described by F. M. Gardner in “A BPSK/QPSK Timing-Error Detector for Sampled Receivers”, IEEE Transactions on Communications, Vol. COM-34, No. 5, May 1986, pp. 423-429.
FIG. 3 shows the output signal of the Gardner phase error detector 300 as a function of the phase error τ 302 expressed as fraction of a period. The curve 301 possesses a horizontal sinusoidal shape and is commonly termed s-curve. Its amplitude or its maximum derivation is termed by Gardner as “phase detector gain” KD indicating the performance quality.
The dynamic behavior of a clock recovery loop as shown in FIG. 2 depends among other parameters on the loop gain which is the product of all amplification factors in the loop, e.g. the loop filter gain Kp, the NCO gain K0 (gain of the numerically controlled oscillator NCO 203), but also the implicit gain of the phase detector KD.
The problem is that the phase detector gain KD and thus the dynamic behavior of the loop depends on the input signal and especially on the distortions present in the input signal. This is undesirable since it makes the loop behavior difficult to analyze and predict.
As shown in J. W. M. Bergmans, “Digital Baseband Transmission and Recording”, Kluwer, 1996 and in F. M. Gardner, “Phaselock Techniques”, 2nd edition, Wiley, 1979, to characterize a second order Phase-Locked Loop PLL only the damping factor ζ and either the natural frequency ωn or the loop bandwidth BL have to be known. From these two parameters all other parameters can be derived:
                                                        ω              n                        ⁢                          T              S                                =                                                    K                f                            ⁢                              K                D                            ⁢                              K                0                                                    ,                                  ⁢                  ζ          =                                    1              2                        ⁢                                                            K                  D                                ⁢                                  K                  0                                ⁢                                                      K                    p                    2                                                        K                    f                                                                                      ,                                  ⁢                                            B              L                        ⁢                          T              S                                =                                    ω              n                        ⁢                                          T                S                            ⁡                              (                                  ζ                  +                                      1                                          4                      ⁢                      ζ                                                                      )                                                                        (        1        )            where the loop filter gain Kp is the amplification factor of the PI-filter in the proportional part and Kf is the amplification factor of the PI-filter in integral part (see FIG. 2), K0 is the oscillator slope, KD is the phase detector slope and TS is the symbol duration. The amplifications Kp, Kf and K0 are fixed parameter, which will not change during transmission, whereas the parameter KD depends mainly on the pulse shape and the power of the received signal, but also on the distortions on the channel due to Differential Group Delay (DGD) and chromatic dispersion (CD). Due to these distortions, KD may vary depending on the transmission conditions. Therefore, it has to be distinguished between KD, design, which is used to design the PLL and KD, signal which results at the Phase Detector (PD) output after transmission. Simulations have shown that due to varying Differential Group Delay (DGD) on the channel the KD, signal at the Phase Detector (PD), output changes and this changes the loop gain of the whole PLL. The impact of changing KD, signal on the parameter of the PLL can be seen in Equation (2). It gives the effective parameters for the case that KD, design=xKD, signal. For KD, signal<KD, design the effective loop bandwidth BL, eff decreases due to the decreasing loop gain and vice versa.
                                                        ζ              eff                        =                                          1                                  x                                            ⁢                              ζ                design                                              ,                                          ⁢                                    ω                              n                ,                eff                                      =                                          1                                  x                                            ⁢                              ω                                  n                  ,                  design                                                              ,                                          ⁢                                    B                              L                ,                eff                                      =                          zB                              L                ,                design                                                    ⁢                                  ⁢        with        ⁢                                  ⁢                  z          =                      (                          1              +                                                                    ζ                    design                                                                              ζ                      design                                        +                                          1                                              4                        ⁢                                                  ζ                          design                                                                                                                    ⁢                                  (                                                            1                      x                                        -                    1                                    )                                                      )                                              (        2        )            
This behavior is a critical point in the design of the clock recovery. The clock recovery has to be stable during the whole transmission even if the loop gain changes. In general there are several limitations for the loop bandwidth BL, eff. The first one is the maximum symbol frequency offset which can be tracked. This limitation can be overcome by use of an active PI-filter which guarantees, in theory, that arbitrarily large symbol frequency offsets ΔfSym can be tracked. Thus, in terms of symbol frequency offset only the pull-in time is a criterion and the lower limit of the loop bandwidth is determined by the desired jitter tolerance. A further limitation is the additional delay in the loop.
As shown in J. W. M. Bergmans, “Effect of Loop Delay on Stability of Discrete-Time PLL”, IEEE Trans. Circuits and Syst. I, Vol. 42, No. 4, pp. 229-231, April 1995, the maximum loop bandwidth for a given additional loop delay of M symbols can be calculated as follows:
                                          B                          L              ,              design                                ⁢          T                <                              1            /                          (                                                2                  ⁢                                      M                    design                                                  +                1                            )                                ⁢                      (                                          ζ                design                            +                              1                                  4                  ⁢                                      ζ                    design                                                                        )                                              (        3        )            
If the effective loop bandwidth BL, eff increases, e.g. due to varying Differential Group Delay (DGD), the PLL may become unstable. The effective maximum tolerable additional loop delay of Meff symbols for KD, design=xKD, signal is:2Meff+1=(2Mdesign+1)√{square root over (x)}  (4)
Conventional clock recovery designs as, for example, described in FIG. 2, usually assume a fully equalized and properly amplified input signal. Deviations of the input signal from these ideal conditions lead to a different than designed dynamic loop behaviour. The “solution” usually is to design the loop for the most probable scenario and restrict the input signal distortions to a limited range. If the distortions exceed this range, however, the loop may take longer than specified to reach the steady state and it may even become unstable and fail completely.
The problem to be solved is to overcome the disadvantages stated above and in particular to provide a solution that allows a stable loop behavior which can be adaptively adjustable.